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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 24M Bits of Internal--On-Chip--DRAM Memory 25 25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks--Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic Unit (CLU) Dual Integer ALUs, providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer Expired Pin for System Integration 1149.1 IEEE Compliant JTAG Test Access Port for OnChip Emulation On-Chip Arbitration for Glueless Multiprocessing
TigerSHARC(R) Embedded Processor ADSP-TS201S
KEY BENEFITS Provides High-Performance Static Superscalar DSP Operations, Optimized for Telecommunications Infrastructure and Other Large, Demanding Multiprocessor DSP Applications Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benchmarks in Table 1) Supports Low-Overhead DMA Transfers Between Internal Memory, External Memory, Memory-Mapped Peripherals, Link Ports, Host Processors, and Other (Multiprocessor) DSPs Eases DSP Programming Through Extremely Flexible Instruction Set and High-Level-Language Friendly DSP Architecture Enables Scalable Multiprocessing Systems With Low Communications Overhead
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS GENERATION INTEGER J ALU PROGRAM SEQUENCER ADDR FETCH J-BUS ADDR J-BUS DATA K-BUS ADDR BTB K-BUS DATA I-BUS ADDR PC I-BUS DATA 32X32 32 32 INTEGER K ALU 32X32 32 128 32
SOC INTERFACE
24M BITS INTERNAL MEMORY MEMORY BLOCKS (PAGE CACHE) 4xCROSSBAR CONNECT A D A D A D A D
SOC BUS JTAG
JTAG PORT 6 EXTERNAL PORT 32 ADDR HOST MULTI PROC SDRAM CTRL C-BUS ARB 64 DATA 8 CTRL 10 CTRL
128 32 128 S-BUS ADDR S-BUS DATA 128 32
EXT DMA REQ 4 DMA LINK PORTS 4 8 4 OUT 8 4 8 IN 4 OUT 8 4 8 IN 4 OUT 8 4 8 IN 4 OUT 8 IN
IAB
T
MULTIPLIER
L0
L1
X REGISTER FILE 32x32
MULTIPLIER
128 128 DAB DAB
128 128 Y REGISTER FILE 32x32
L2
SHIFTER
SHIFTER
ALU
CLU
ALU
CLU
L3
COMPUTATIONAL BLOCKS
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. REV. PrG
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c) Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA ADSP-TS201S
TABLE OF CONTENTS
For current information contact Analog Devices at 800/262-5643
June 2003
GENERAL DESCRIPTION
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Dual Compute Blocks . . . . . . . . . . . . . . . . . . . . . . . . 3 Data Alignment Buffer (DAB) . . . . . . . . . . . . . . . . . . 4 Dual Integer ALUs (IALUs) . . . . . . . . . . . . . . . . . . . 4 Program Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 4 Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 4 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 External Port (Off-Chip Memory/Peripherals Interface) . . . . . . 6 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Multiprocessor Interface . . . . . . . . . . . . . . . . . . . . . 6 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . 6 EPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 7 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Link Ports (LVDS) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timer and General-Purpose I/O . . . . . . . . . . . . . . . . 8 Reset and Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Filtering Reference Voltage and Clocks . . . . . . . . . . . 9 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Designing an Emulator-Compatible DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Additional Information . . . . . . . . . . . . . . . . . . . . . . 11 Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . 11 Strap Pin Function Descriptions . . . . . . . . . . . . . . . . . 18 ADSP-TS201S--Specifications . . . . . . . . . . . . . . . . . . 20 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 21 ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 21 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 21 General AC Timing . . . . . . . . . . . . . . . . . . . . . . . 21 Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing . . . . . . . 26 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 31 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Output Disable Time . . . . . . . . . . . . . . . . . . . . . . 32 Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 32 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 33 Environmental Conditions . . . . . . . . . . . . . . . . . . . . 34 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 34 576-Ball BGA_ED Pin Configurations . . . . . . . . . . . . 36 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
The ADSP-TS201S TigerSHARC processor is an ultra-high performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks--supporting 32- and 40-bit floating-point and supporting 8-, 16-, 32-, and 64-bit fixed-point processing--to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing twenty-four 16-bit fixed-point operations or six floating-point operations. Four independent 128-bit wide internal data buses, each connecting to the six 4M bit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS201S processor's core has a 2.0 ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) features, the ADSP-TS201S processor can perform four billion 40-bit MACs or one billion 80-bit MACs per second. Table 1 shows the DSP's performance benchmarks.
Table 1. General Purpose Algorithm Benchmarks at 500 MHz Benchmark Speed Clock Cycles
32-bit Algorithm, 500 million MACs/s peak performance 10061 1024 Point Complex FFT1 (Radix2) 20 s FIR Filter (per real tap) 1 ns 0.5 [8 x 8][8 x 8] Matrix Multiply 2.8 s 1399 (Complex, Floating-point) 16-bit Algorithm, 2 billion MACs/s peak performance 256 Point Complex FFT1 (Radix 2) 1.9 s 928 I/O DMA Transfer Rate External port 1G bytes/s n/a Link ports (each) 1G bytes/s n/a
1
Cache preloaded
The ADSP-TS201S processor is code-compatible with the other TigerSHARC processors. The Functional Block Diagram on page 1 shows the ADSPTS201S processor's architectural blocks. These blocks include: * Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, 128-bit CLU, and 32-word register file and associated Data Alignment Buffers (DABs) * Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing and a status register * A program sequencer with Instruction Alignment Buffer (IAB) and Branch Target Buffer (BTB) * An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts
2
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PRELIMINARY TECHNICAL DATA June 2003
* On-chip DRAM (24M bit) * An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM * A 14 channel DMA controller * Four full-duplex LVDS link ports * Two 64-bit interval timers and timer expired pin * A 1149.1 IEEE compliant JTAG test access port for onchip emulation Figure 1 on page 3 shows a typical single-processor system with external SRAM and SDRAM. Figure 3 on page 7 shows a typical multiprocessor system.
ADSP-TS201S
RST_IN RST_OUT POR_IN CLOCK REFERENCE REFERENCE
SDRAM MEMORY (OPTIONAL) BOOT EPROM (OPTIONAL)
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ADSP-TS201S
* Four 128-bit internal data buses, each connecting to the six 4M bit memory banks
the DSP does not perform instruction re-ordering at runtime-- the programmer selects which operations will execute in parallel prior to runtime--the order of instructions is static. With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a ten-deep processor pipeline. For optimal DSP program execution, programmers must follow the DSP's set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the DSP can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. The programmer has direct control of three core components--the IALUs, the compute blocks, and the program sequencer. The ADSP-TS201S processor, in most cases, has a two-cycle execution pipeline that is fully interlocked, so--whenever a computation result is unavailable for another operation dependent on it--the DSP automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies. In addition, the ADSP-TS201S processor supports SIMD operations two ways--SIMD compute blocks and SIMD computations. The programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution).
Dual Compute Blocks
SCLK SCLKRAT2-0 SCLK_VREF VREF IRQ3-0 FLAG3-0 ID2-0 MSSD3-0 RAS CAS LDQM HDQM SDWE SDCKE
BMS
CS ADDR
BRST ADDR31-0 DATA63-0 RD WRH/WRL ACK MS1-0 MSH HBR HBG BOFF
DATA
MEMORY (OPTIONAL)
ADDR DATA OE WE ACK CS
HOST PROCESSOR INTERFACE (OPTIONAL)
CLK CS ADDR RAS DATA CAS DQM WE CKE A10
LxACKO LxBCMPI CONTROLIMP1-0 BM BUSLOCK TMR0E DS2-0 JTAG
CONTROL
ADDRESS
DATA
LINK DEVICES (4 MAX) (OPTIONAL)
SDA10 BR7-0 IORD CPA IOWR DPA IOEN LxDATO3-0P/N LxCLKOUTP/N DMAR3-0 LxACKI LxBCMPO LxDATI3-0P/N LxCLKINP/N
ADDR DATA
DMA DEVICE (OPTIONAL)
The ADSP-TS201S processor has compute blocks that can execute computations either independently or together as a Single-Instruction, Multiple-Data (SIMD) engine. The DSP can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, shifter, or CLU to perform independent, simultaneous operations. Each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with the operation in the other block. The compute blocks are referred to as X and Y in assembly syntax, and each block contains four computational units--an ALU, a multiplier, a 64-bit shifter, a 128-bit CLU--and a 32word register file. * Register File--Each Compute Block has a multiported 32-word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (wordaligned), in sets of two (dual-aligned), or in sets of four (quad-aligned). * ALU--The ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic operations. * Multiplier--The multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate.
DATA
Figure 1. ADSP-TS201S Single-Processor System With External SDRAM
The TigerSHARC DSP uses a Static Superscalar1 architecture. This architecture is superscalar in that the ADSP-TS201S processor's core can execute simultaneously from one to four 32-bit instructions encoded in a Very Large Instruction Word (VLIW) instruction line using the DSP's dual compute blocks. Because
1
Static SuperscalarTM is a trademark of Analog Devices, Inc.
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PRELIMINARY TECHNICAL DATA ADSP-TS201S
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June 2003
* Shifter--The 64-bit shifter performs logical and arithmetic shifts, bit and bitstream manipulation, and field deposit and extraction operations. * Communications Logic Unit (CLU)--This is a 128-bit unit provides Trellis Decoding (for example, Viterbi and Turbo decoders) and executes complex correlations for CDMA communication applications (for example chiprate and symbol-rate functions). Using these features, the compute blocks can: * Provide 8 MACs per cycle peak and 7.1 MACs per cycle sustained 16-bit performance and provide 2 MACs per cycle peak and 1.8 MACs per cycle sustained 32-bit performance (based on FIR) * Execute six single-precision floating-point or execute twenty-four 16-bit fixed-point operations per cycle, providing 3 GFLOPS or 12.0 GOPS performance * Perform two complex 16-bit MACs per cycle * Execute eight Trellis butterflies in one cycle
Data Alignment Buffer (DAB)
Because the IALU's computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is unavailable in a given cycle.
Program Sequencer
The ADSP-TS201S processor's program sequencer supports the following: * A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles * A ten-cycle instruction pipeline--four-cycle fetch pipe and six-cycle execution pipe--computation results available two cycles after operands are available * Supply of instruction fetch memory addresses; the sequencer's Instruction Alignment Buffer (IAB) caches up to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution * Management of program structures and program flow determined according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software exceptions * Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches that are taken occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty * Compact code without the requirement to align code in memory; the IAB handles alignment
Interrupt Controller
The DAB is a quad-word FIFO that enables loading of quadword data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR filters.
Dual Integer ALUs (IALUs)
The ADSP-TS201S processor has two IALUs that provide powerful address generation capabilities and perform many general-purpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features: * Provides memory addresses for data and update pointers * Supports circular buffering and bit-reverse addressing * Performs general-purpose integer operations, increasing programming flexibility * Includes a 31-word register file for each IALU As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each IALU can specify either a single-, dual-, or quad-word access from memory. The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location.
The DSP supports nested and nonnested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level-sensitive or edge-sensitive, except the IRQ3-0 hardware interrupts, which are programmable. The DSP distinguishes between hardware interrupts and software exceptions, handling them differently. When a software exception occurs, the DSP aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the DSP continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the DSP to conditionally execute a multiply, an add, and
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ADSP-TS201S
a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include: * CLU instructions for communications infrastructure to govern Trellis Decoding (for example, Viterbi and Turbo decoders) and Despreading via complex correlations * Algebraic assembly language syntax * Direct support for all DSP, imaging, and video arithmetic types * Eliminates toggling DSP hardware modes because modes are supported as options (for example, rounding, saturation, and others) within instructions
* Branch prediction encoded in instruction; enables zerooverhead loops * Parallelism encoded in instruction line * Conditional execution optional for all instructions * User defined partitioning between program and data memory
DSP Memory
The DSP's internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in Figure 2. The memory map is divided into four memory areas--host space, external memory, multiprocessor space, and internal memory-- and each memory space, except host memory, is subdivided into smaller memory spaces.
GLOBAL SPACE
0xFFFFFFFF
HOST (MSH)
0x80000000 RESERVED 0x74000000 MSSD BANK 3 (MSSD3) 0x70000000 0x03FFFFFF
EXTERNAL MEMORY SPACE
INTERNAL SPACE
RESERVED 0x64000000 MSSD BANK 2 (MSSD2) 0x60000000 RESERVED 0x54000000 MSSD BANK 1 (MSSD1) 0x50000000 RESERVED 0x44000000 MSSD BANK 0 (MSSD0) 0x40000000 BANK 1 (MS1) 0x38000000 BANK 0 (MS0) 0x30000000
MULTIPROCESSOR MEMORY SPACE
RESERVED
0x001F03FF SOC REGISTERS (UREGS) RESERVED 0x001E03FF INTERNAL REGISTERS (UREG S) RESERVED INTERNAL MEMO RY BL OCK 10 RESERVED 0x0011FFFF INTERNAL MEMO RY BLOCK 8 RESERVED INTERNAL MEMORY BLOCK 6 RESERVED INTERNAL MEMORY BLOCK 4 RESERVED INTERNAL MEMORY BLOCK 2 0x00040000 RESERVED 0x0001FFFF INTERNAL MEMORY BLOCK 0 0x00000000 INTERNAL MEMORY 0x00100000 0x000DFFFF 0x000C0000 0x0009FFFF 0x00080000 0x0005FFFF RESERVED 0X001E0000 0x0015FFFF 0x00140000 PROCESSOR ID 7 0X001F0000
0x2C000000 PROCESSOR ID 6 0x28000000 PROCESSOR ID 5 0x24000000 PROCESSOR ID 4 0x20000000 PROCESSOR ID 3 0x1C000000 PROCESSOR ID 2 0x18000000 PROCESSOR ID 1 0x14000000 PROCESSOR ID 0 0x10000000 BROADCAST 0X0C000000 EACH IS A COPY OF INTERNAL SPACE
0x03FFFFFF 0x00000000
Figure 2. ADSP-TS201S Memory Map
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PRELIMINARY TECHNICAL DATA ADSP-TS201S
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June 2003
The ADSP-TS201S processor internal memory has 24M bits of on-chip DRAM memory, divided into six blocks of 4M bits (128K words x 32 bits). Each block--M0, M2, M4, M6, M8, and M10--can store program, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the DSP to access data while performing an instruction fetch. Each memory segment contains a 128K bit cache to enable single cycle accesses to internal DRAM. The six internal memory blocks connect to the four 128-bit wide internal buses through a crossbar connection, enabling the DSP to perform four memory transfers in the same cycle. The DSP's internal bus architecture provides a total memory bandwidth of 28G bytes per second, enabling the core and I/O to access eight 32-bit data words and four 32-bit instructions each cycle. The DSP's flexible memory structure enables: * DSP core and I/O accesses to different memory blocks in the same cycle * DSP core access to three memory blocks in parallel--one instruction and two data accesses * Programmable partitioning of program and data memory * Program access of all memory as 32-, 64-, or 128-bit words--16-bit words with the DAB
External Port (Off-Chip Memory/Peripherals Interface)
the host interface supports pipelined or slow protocols for ADSPTS201S processor accesses of the host as slave or pipelined for host accesses of the ADSP-TS201S processor as slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles. The host interface supports burst transactions initiated by a host processor. After the host issues the starting address of the burst and asserts the BRST signal, the DSP increments the address internally while the host continues to assert BRST. The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the DSP. The BOFF signal provides the deadlock recovery mechanism. When the host asserts BOFF, the DSP backs off the current transaction and asserts HBG and relinquishes the external bus. The host can directly read or write the internal memory of the ADSP-TS201S processor, and it can access most of the DSP registers, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS201S processor offers powerful features tailored to multiprocessing DSP systems through the external port and link ports. This multiprocessing capability provides highest bandwidth for interprocessor communication, including: * Up to eight DSPs on a common bus * On-chip arbitration for glueless multiprocessing * Link ports for point to point communication The external port and link ports provide integrated, glueless multiprocessing support. The external port supports a unified address space (see Figure 2) that enables direct interprocessor accesses of each ADSPTS201S processor's internal memory and registers. The DSP's on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight ADSP-TS201S processors and a host processor. Bus arbitration has a rotating priority. Bus lock supports indivisible read-modify-write sequences for semaphores. A bus fairness feature prevents one DSP from holding the external bus too long. The DSP's four link ports provide a second path for interprocessor communications with throughput of 4G bytes per second. The cluster bus provides 1G bytes per second throughput--with a total of 4G bytes per second interprocessor bandwidth (limited by SOC bandwidth).
SDRAM Controller
The ADSP-TS201S processor's external port provides the DSP's interface to off-chip memory and peripherals. The 4G word address space is included in the DSP's unified address space. The separate on-chip buses--four 128-bit data buses and four 32-bit address buses--are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction. The external system bus provides a single 64-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 1G bytes per second over the external bus. The external bus can be configured for 32- or 64-bit, little-endian operations. When the system bus is configured for 64-bit operations, the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses. The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of highorder address lines to generate memory bank select signals. The ADSP-TS201S processor provides programmable memory, pipeline depth, and idle cycle for synchronous accesses, and external acknowledge controls to support interfacing to pipelined or slow devices, host processors, and other memory-mapped peripherals with variable access, hold, and disable time requirements.
Host Interface
The SDRAM controller controls the ADSP-TS201S processor's transfers of data to and from external synchronous DRAM (SDRAM) at a throughput of 32 or 64 bits per SCLK cycle using the external port and SDRAM control pins.
The ADSP-TS201S processor provides an easy and configurable interface between its external bus and host processors through the external port. To accommodate a variety of host processors, 6
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CONTROL
ADDRESS ADDRESS
ADSP-TS201S #1 001 ID2-0 RST_IN CLKS/REFS LINK DEVICES LINK BR7-2,0 BR1 ADDR31-0 DATA63-0 CONTROL
CONTROL
000 RESET
ID2-0 RST_IN CLKS/REFS RST_OUT POR_IN
BR7-1 BR0 ADDR31-0 DATA63-0 RD WRH/L ACK MS1-0 BUSLOCK BMS CPA DPA BRST DMAR3-0 BOFF HBR HBG MSH IORD IOWR IOEN MSSD3-0 RAS CAS LDQM HDQM SDWE SDCKE SDA10 CONTROL
DATA
ADSP-TS201S #0
DATA
ADSP-TS201S #7 ADSP-TS201S #6 ADSP-TS201S #5 ADSP-TS201S #4 ADSP-TS201S #3 ADSP-TS201S #2
ADDR DATA OE WE ACK CS CS ADDR DATA GLOBAL MEMORY AND PERIPHERALS (OPTIONAL)
CLOCK
SCLK
REFERENCE REFERENCE
SCLK_VREF VREF SCLKRAT2-0
BOOT EPROM (OPTIONAL) CLOCK
IRQ3-0 FLAG3-0 LINK LxDATO3-0P/N LxCLKOUTP/N LINK DEVICES (4 MAX) (OPTIONAL) LxACKI LxBCMPO LxDATI3-0P/N LxCLKINP/N LxACKO LxBCMPI TMR0E BM CONTROLIMP1-0 DS2-0 JTAG
ADDR DATA CS RAS CAS DQM WE CKE A10 ADDR DATA
HOST PROCESSOR INTERFACE (OPTIONAL)
SDRAM MEMORY (OPTIONAL)
CLK
Figure 3. ADSP-TS201S Shared Memory Multiprocessing System
The SDRAM interface provides a glueless interface with standard SDRAMs--16M bit, 64M bit, 128M bit, and 256M bit. The DSP supports directly a maximum of four banks of 64M words x 32 bit of SDRAM. The SDRAM interface is mapped in external memory in each DSP's unified memory map.
EPROM Interface
procedure uses DMA channel 0, which packs the bytes into 32bit instructions. Applications can also access the EPROM (write flash memories) during normal operation through DMA. The EPROM or Flash Memory interface is not mapped in the DSP's unified memory map. It is a byte address space limited to a maximum of 16M bytes (twenty-four address bits). The EPROM or Flash Memory interface can be used after boot via a DMA.
DMA Controller
The ADSP-TS201S processor can be configured to boot from an external 8-bit EPROM at reset through the external port. An automatic process (which follows reset) loads a program from the EPROM into internal memory. This process uses sixteen wait cycles for each read access. During booting, the BMS pin functions as the EPROM chip select signal. The EPROM boot
The ADSP-TS201S processor's on-chip DMA controller, with 14 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates indepen7
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PRELIMINARY TECHNICAL DATA ADSP-TS201S
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dently and invisibly to the DSP's core, enabling DMA operations to occur while the DSP's core continues to execute program instructions. The DMA controller performs DMA transfers between internal memory and external memory and memory-mapped peripherals, the internal memory of other DSPs on a common bus, a host processor, or link port I/O; between external memory and external peripherals or link port I/O; and between an external bus master and internal memory or link port I/O. The DMA controller performs the following DMA operations: * External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the DSP's internal memory and any external memory or memory-mapped peripheral on the external bus. These transfers support master mode and handshake mode protocols. * Link port transfers. Eight dedicated DMA channels (four transmit and four receive) transfer quad-word data only between link ports and between a link port and internal or external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels. * AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer. The DMA controller provides these additional features: * Flyby transfers. Flyby operations only occur through the external port (DMA channel 0) and do not involve the DSP's core. The DMA controller acts as a conduit to transfer data from an I/O device to external SDRAM memory. During a transaction, the DSP relinquishes the external data bus; outputs addresses, memory selects (MSSD3-0) and the IORD, IOWR, IOEN, and RD/WR strobes; and responds to ACK. * DMA chaining. DMA chaining operations enable applications to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes. * Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions.
Link Ports (LVDS)
and falling edges of the clock--running at 500 MHz, each link port can support up to 500M bytes per second per direction, for a combined maximum throughput of 4G bytes per second. The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing point-topoint interprocessor communications. Applications can also use the link ports for booting. Each link port has its own triple-buffered quad-word input and double-buffered quad-word output registers. The DSP's core can write directly to a link port's transmit register and read from a receive register, or the DMA controller can perform DMA transfers through eight (four transmit and four receive) dedicated link port DMA channels. Each link port direction has three signals that control its operation. For the transmitter, LxCLKOUT is the output transmit clock, LxACKI is the handshake input to control the data flow, and the LxBCMPO output indicates that the block transfer is complete. For the receiver, LxCLKIN is the input receive clock, LxACKO is the handshake output to control the data flow, and the LxBCMPI input indicates that the block transfer is complete. The LxDATO3-0 pins are the data output bus for the transmitter and the LxDATI3-0 pins are the input data bus for the receiver. Applications can program separate error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are transmitted.
Timer and General-Purpose I/O
The ADSP-TS201S processor has a timer pin (TMR0E) that generates output when a programmed timer counter has expired and four programmable general-purpose I/O pins (FLAG3-0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching.
Reset and Booting
The ADSP-TS201S processor has three levels of reset: * Power-up reset--After power-up of the system (SCLK, all static inputs, and strap pins are stable), the RST_IN pin must be asserted (low). * Normal reset--For any chip reset following the power-up reset, the RST_IN pin must be asserted (low). * DSP-core reset--When setting the SWRST bit in EMUCTL, the DSP core is reset, but not the external port or I/O. For normal operations, tie the RST_OUT pin to the POR_IN pin. After reset, the ADSP-TS201S processor has four boot options for beginning operation: * Boot from EPROM. * Boot by an external master (host or another ADSPTS201S processor). REV. PrG
The DSP's four full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using LowVoltage, Differential-Signal (LVDS) technology. With the ability to operate at a double data rate--latching data on both the rising
8
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PRELIMINARY TECHNICAL DATA June 2003
* Boot by link port. * No boot--Start running from memory address selected with one of the IRQ3-0 interrupt signals. See Table 2. Using the `no boot' option, the ADSP-TS201S processor must start running from memory when one of the interrupts is asserted.
Table 2. No Boot, Run From Memory Addresses Interrupt Address
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Note that the analog (VDD_A) supply powers the clock generator PLLs. To produce a stable clock, systems must provide a clean power supply to power input VDD_A. Designs must pay critical attention to bypassing the VDD_A supply.
Filtering Reference Voltage and Clocks
Figure 5 and Figure 6 show possible circuits for filtering VREF, and SCLK_VREF. These circuits provide the reference voltages for the switching voltage reference and system clock reference.
VDD_IO VREF
IRQ0 IRQ1 IRQ2 IRQ3
0x3000 0000 (External Memory) 0x3800 0000 (External Memory) 0x8000 0000 (External Memory) 0x0000 0000 (Internal Memory)
R1 R2 C1 C2
The ADSP-TS201S processor core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset. For more information on boot options, see the EE-174: ADSPTS101S Booting Methods on the Analog Devices website (www.analog.com)
Clock Domains
VSS R1: 2 k SERIES RESISTOR (1%) R2: 2 k SERIES RESISTOR (1%) C1: 1 F CAPACITOR (SMD) C2: 1 nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP'S PINS
Figure 5. VREF filtering scheme
CLOCK DRIVER VOLTAGE * OR V DD_IO R1 R2 C1 C2
The DSP uses calculated ratios of the SCLK clock to operate as shown in Figure 4. The instruction execution rate is equal to CCLK. A PLL from SCLK generates CCLK which is phaselocked. The SCLKRATx pins define the clock multiplication of SCLK to CCLK (see Table 4 on page 11). The link port clock is generated from CCLK via a software programmable divisor, and the SOC bus operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. SCLK also provides clock input for the external bus interface and defines the AC specification reference for the external bus signals. The external bus interface runs at the SCLK frequency. The maximum SCLK frequency is one quarter the internal DSP clock (CCLK) frequency.
SCLK_VREF
VSS R1: 2 k SERIES RESISTOR (1%) R2: 2 k SERIES RESISTOR (1%) C1: 1 F CAPACITOR (SMD) C2: 1 nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP'S PINS * IF CLOCK DRIVER VOLTAGE VDD_IO
Figure 6. SCLK_VREF filtering scheme Development Tools
EXTERNAL INTERFACE SCLK SCLKRATx PLL /2 /CR SPD BITS, LCTLx REGISTER CCLK (INSTRUCTION RATE) SOCCLK (PERIPHERAL BUS RATE) LxCLKOUT (LINK OUTPUT RATE)
The ADSP-TS201S processor is supported with a complete set of CROSSCORE2 software and hardware development tools, including Analog Devices emulators and VisualDSP++3 development environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS201S processor. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for theses tools is C/C++ code
Figure 4. Clock Domains Power Domains
The ADSP-TS201S processor has separate power supply connections for internal logic (VDD), analog circuits (VDD_A), I/O buffer (VDD_IO), and internal DRAM (VDD_DRAM) power supply.
2 3
CROSSCORE is a trademark of Analog Devices, Inc. VisualDSP++ is a trademark of Analog Devices, Inc.
REV. PrG
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the realtime characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert breakpoints * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Perform source level debugging * Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permit programmers to: * Control how the development tools process inputs and generate outputs * Maintain a one-to-one correspondence with the tool's command line switches The VisualDSP++TM Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Preemptive, Cooperative and Time -Sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++TM development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. VCSE is Analog Devices' technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into the application. Publish component archives from within VisualDSP++TM. VCSE supports component implementation in C/C++ or assembly language. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with the drag of the mouse, examine run-time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-TS201S processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the TigerSHARC processor family. Hardware tools include TigerSHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.
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To use these emulators, the target board must include a header that connects the DSP's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)--use site search on "EE-68". This document is updated regularly to keep pace with improvements to emulator support.
Additional Information
Programming Reference. For detailed information on the development tools for this processor, see the VisualDSP++ User's Guide for TigerSHARC Processors.
PIN FUNCTION DESCRIPTIONS
This data sheet provides a general overview of the ADSP-TS201S processor's architecture and functionality. For detailed information on the ADSP-TS201S processor's core architecture and instruction set, see the ADSP-TS201 TigerSHARC Processor Hardware Reference and the ADSP-TS201 TigerSHARC Processor
While most of the ADSP-TS201S processor's input pins are normally synchronous--tied to a specific clock--a few are asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. Use the AC specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals. The output pins can be three-stated during normal operation. The DSP three-states all outputs during reset, allowing these pins to get to their internal pullup or pulldown state. Some pins have an internal pullup or pulldown resistor (30% tolerance) that maintains a known value during transitions between different drivers.
Table 3. Pin Definitions--Clocks and Reset Signal Type Description
SCLKRAT2-0
I (pd)
SCLK
I1
RST_IN
I/A
RST_OUT POR_IN
O I/A
Core Clock Ratio. The DSP's core clock (CCLK) rate = n x SCLK, where n is userprogrammable using the SCLKRATx pins to the values shown in Table 4. These pins must have a constant value while the DSP is powered. The core clock rate (CCLK) is the instruction cycle rate. System Clock Input. The DSP's system input clock for cluster bus.The core clock rate is user-programmable using the SCLKRATx pins. For more information, see Clock Domains on page 9. Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN must be asserted a specified time according to the type of reset operation. For details, see Reset and Booting on page 8, Table 19 on page 22, and Figure 9 on page 23. Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN. Power On Reset for internal DRAM. Connect to RST_OUT.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
1
For more information on SCLK and SCLK_VREF on revision 0.0 silicon, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com).
Table 4. SCLK Ratio SCLKRAT2-0 Ratio
000 001 010 011 100 101 110 111
(default)
4 5 6 7 8 10 12 Reserved
REV. PrG
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Table 5. Pin Definitions--External Port Bus Controls Description
ADDR31-0
I/O/T (pu_ad)
DATA63-0 RD
I/O/T (pu_ad) I/O/T (pu_0)
WRL
I/O/T (pu_0)
WRH
I/O/T (pu_0)
ACK
I/O/T/OD (pu_od_0)
BMS
O/T (pu_0)
MS1-0
O/T (pu_0)
MSH
O/T (pu_0) I/O/T (pu_0)
BRST
Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS201S processors. The DSP inputs addresses when a host or another DSP accesses its internal memory or I/O processor registers. External Data Bus. The DSP drives and receives data and instructions on these pins. Pullup/down resistors on unused DATA pins are unnecessary. Memory Read. RD is asserted whenever the DSP reads from any slave in the system, excluding SDRAM. When the DSP is a slave, RD is an input and indicates read transactions that access its internal memory or universal registers. In a multiprocessor system, the bus master drives RD. RD changes concurrently with ADDR pins. Write Low. WRL is asserted in two cases: When the ADSP-TS201S processor writes to an even address word of external memory or to another external bus agent; and when the ADSP-TS201S processor writes to a 32-bit zone (host, memory or DSP programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing to a DSP's low word of internal memory. In a multiprocessor system, the bus master drives WRL. WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL is an input and indicates write transactions that access its internal memory or universal registers. Write High. WRH is asserted when the ADSP-TS201S processor writes a long word (64 bits) or writes to an odd address word of external memory or to another external bus agent on a 64-bit data bus. An external master (host or another DSP) must assert WRH for writing to a DSP's high word of 64-bit data bus. In a multiprocessing system, the bus master drives WRH. WRH changes concurrently with ADDR pins. When the DSP is a slave, WRH is an input and indicates write transactions that access its internal memory or universal registers. Acknowledge. External slave devices can de-assert ACK to add wait states to external memory accesses. ACK is used by I/O devices, memory controllers and other peripherals on the data phase. The DSP can de-assert ACK to add wait states to read and write accesses of its internal memory. The pullup is 50 on low-to-high transactions and is 500 on all other transactions. Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multiprocessor system, the DSP bus master drives BMS. For details, see Reset and Booting on page 8 and see the EBOOT signal description in Table 15 on page 18. Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0 or 1 respectively. MS1-0 are decoded memory address pins that change concurrently with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When ADDR31:27 = 0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1-0. Memory Select Host. MSH is asserted whenever the DSP accesses the host address space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes concurrently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH. Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading or writing data associated with consecutive addresses. A slave device can ignore addresses after the first one and increment an internal address counter after each transfer. For host-to-DSP burst accesses, the DSP increments the address automatically while BRST is asserted.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
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Table 6. Pin Definitions--External Port Arbitration Description
BR7-0
I/O
ID2-0
I (pd)
BM BOFF
O I
BUSLOCK HBR
O/T (pu_0) I
HBG
I/O/T (pu_0)
CPA
I/O/OD (pu_od_0)
DPA
I/O/OD (pu_od_0)
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In systems with fewer than eight DSPs, set the unused BRx pins high (VDD_IO). Multiprocessor ID. Indicates the DSP's ID, from which the DSP determines its order in a multiprocessor system. These pins also indicate to the DSP which bus request (BR0-BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2-0 must have a constant value during system operation and can change during reset only. Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this is a strap pin. For more information, see Table 15 on page 18. Back Off. A deadlock situation can occur when the host and a DSP try to read from each other's bus at the same time. When deadlock occurs, the host can assert BOFF to force the DSP to relinquish the bus before completing its outstanding transaction. Bus Lock Indication. Provides an indication that the current bus master has locked the bus. At reset, this is a strap pin. For more information, see Table 15 on page 18. Host Bus Request. A host must assert HBR to request control of the DSP's external bus. When HBR is asserted in a multiprocessing system, the bus master relinquishes the bus and asserts HBG once the outstanding transaction is finished. Host Bus Grant. Acknowledges HBR and indicates that the host can take control of the external bus. When relinquishing the bus, the master DSP three-states the ADDR31-0, DATA63-0, MSH, MSSD3-0, MS1-0, RD, WRL, WRH, BMS, BRST, IORD, IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM and HDQM pins, and the DSP puts the SDRAM in self-refresh mode. The DSP asserts HBG until the host deasserts HBR. In multiprocessor systems, the current bus master DSP drives HBG, and all slave DSPs monitor it. Core Priority Access. Asserted while the DSP's core accesses external memory. This pin enables a slave DSP to interrupt a master DSP's background DMA transfers and gain control of the external bus for core-initiated transactions. CPA is an open drain output, connected to all DSPs in the system. If not required in the system, leave CPA unconnected (external pullups will be required for DSP ID=1 through ID=7). DMA Priority Access. Asserted while a high-priority DSP DMA channel accesses external memory. This pin enables a high-priority DMA channel on a slave DSP to interrupt transfers of a normal-priority DMA channel on a master DSP and gain control of the external bus for DMA-initiated transactions. DPA is an open drain output, connected to all DSPs in the system. If not required in the system, leave DPA unconnected (external pullups will be required for DSP ID=1 through ID=7).
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
REV. PrG
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Table 7. Pin Definitions--External Port DMA/Flyby Description
DMAR3-0
I/A
IOWR
O/T (pu_0) O/T (pu_0) O/T (pu_0)
IORD
IOEN
DMA Request Pins. Enable external I/O devices to request DMA services from the DSP. In response to DMARx, the DSP performs DMA transfers according to the DMA channel's initialization. The DSP ignores DMA requests from uninitialized channels. I/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP asserts the IOWR signal during the data cycles. This assertion makes the I/O device sample the data instead of the TigerSHARC. I/O Read. When a DSP DMA channel initiates a flyby mode write transaction, the DSP asserts the IORD signal during the data cycle. This assertion with the IOEN makes the I/O device drive the data instead of the TigerSHARC. I/O Device Output Enable. Enables the output buffers of an external I/O device for flyby transactions between the device and external memory. Active on fly-by transactions.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
Table 8. Pin Definitions--External Port SDRAM Controller Signal Type Description
MSSD3-0
I/O/T (pu_0)
RAS
I/O/T (pu_0) I/O/T (pu_0) O/T (pu_0)
CAS
LDQM
HDQM
O/T (pu_0)
Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the DSP accesses SDRAM memory space. MSSD3-0 are decoded memory address pins that are asserted whenever the DSP issues an SDRAM command cycle (access to ADDR31:30 = 0b01--except reserved spaces shown in Figure 2 on page 5). In a multiprocessor system, the master DSP drives MSSD3-0. Row Address Select. When sampled low, RAS indicates that a row address is valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to SDRAM specification. Column Address Select. When sampled low, CAS indicates that a column address is valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to the SDRAM specification. Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ buffers. LDQM is valid on SDRAM transactions when CAS is asserted, and inactive on read transactions. On write transactions, LDQM is active when accessing an odd address word on a 64-bit memory bus to disable the write of the low word. High Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ buffers. HDQM is valid on SDRAM transactions when CAS is asserted, and inactive on read transactions. On write transactions, HDQM is active when accessing an even address in word accesses or when memory is configured for a 32-bit bus to disable the write of the high word.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
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Table 8. Pin Definitions--External Port SDRAM Controller (continued) Description
SDA10 SDCKE
O/T (pu_0) I/O/T (pu_m/ pd_m)
SDWE
I/O/T (pu_0)
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation while the DSP executes non-SDRAM transactions. SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend modes. A slave DSP in a multiprocessor system does not have the pullup or pulldown. A master DSP (or ID=0 in a single processor system) has a pullup before granting the bus to the host, except when the SDRAM is put in self refresh mode. In self refresh mode, the master has a pulldown before granting the bus to the host. SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an SDRAM write access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM specification.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
Table 9. Pin Definitions--JTAG Port Signal Type Description
EMU TCK TDI TDO TMS TRST
O/OD I I (pu_ad) O/T I (pu_ad) I/A (pu_ad)
Emulation. Connected to the DSP's JTAG emulator target board connector only. Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. Test Data Input (JTAG). A serial data input of the scan path. Test Data Output (JTAG). A serial data output of the scan path. Test Mode Select (JTAG). Used to control the test state machine. Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low after power up for proper device operation. For more information, see Reset and Booting on page 8.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20
Table 10. Pin Definitions--Flags, Interrupts, and Timer Signal Type Description
FLAG3-0
I/O/A (pu) I/A (pu)
IRQ3-0
TMR0E
O
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be configured individually for input or for output. FLAG3-0 are inputs after power-up and reset. Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3-0 pins can be independently set for edge-triggered or level-sensitive operation. After reset, these pins are disabled unless the IRQ3-0 strap option and interrupt vectors are initialized for booting. Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin. For more information, see Table 15 on page 18.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
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Table 11. Pin Definitions--Link Ports Description
LxDATO3-0P LxDATO3-0N LxCLKOUTP LxCLKOUTN LxACKI LxBCMPO
O O O O I (pd) O
LxDATI3-0P LxDATI3-0N LxCLKINP LxCLKINN LxACKO LxBCMPI
I I I/A I/A O I
Link Ports 3-0 Data 3-0 Transmit LVDS P Link Ports 3-0 Data 3-0 Transmit LVDS N Link Ports 3-0 Transmit Clock LVDS P Link Ports 3-0 Transmit Clock LVDS N Link Ports 3-0 Receive Acknowledge. Using this signal, the receiver indicates to the transmitter that it may continue the transmission Link Ports 3-0 Block Completion. When the transmission is executed using DMA, this signal indicates to the receiver that the transmitted block is completed. At reset, the L1BCMPO, L2BCMPO, and L3BCMPO pins are strap pins. For more information, see Table 15 on page 18. Link Ports 3-0 Data 3-0 Receive LVDS P Link Ports 3-0 Data 3-0 Receive LVDS N Link Ports 3-0 Receive Clock LVDS P Link Ports 3-0 Receive Clock LVDS N Link Ports 3-0 Transmit Acknowledge. Using this signal, the receiver indicates to the transmitter that it may continue the transmission. Link Ports 3-0 Block Completion. When the reception is executed using DMA, this signal indicates to the transmitter that the receive block is completed.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
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Table 12. Pin definitions--Impedance Control , Drive Strength Control, and Regulator Enable Description
CONTROLIMP0
I (pd)
CONTROLIMP1
I (pu)
DS2,0 DS1
I (pu) I (pd)
ENEDREG
I (pu)
Impedance Control. CONTROLIMP0 enables Pulse Mode. When CONTROLIMP0 = 0, Pulse Mode is disabled and the output drive strength is continuously controlled by DS2-0, both in the digital mode and in the analog mode (See analog and digital modes below). When CONTROLIMP0 = 1, Pulse Mode is enabled. In Pulse Mode, whenever a new value is driven to the output pin, drive strength is set to 100% for a short period of 1.5-2.5ns after rising edge of SCLK and afterwards it is set back to the value defined by the resistance control DS2-0 pins as shown in Table 13. Impedance Control. CONTROLIMP1 enables A/D mode of the control impedance circuitry.When CONTROLIMP1 = 0, A/D mode is disabled, and output drive strength is set relative to maximum drive strength according to table in DS2-0 explanation. When CONTROLIMP1 = 1, A/D mode is enabled, and the resistance control operates in the analog mode, where drive strength is continuously controlled to match a specific line impedance as shown in Table 13. Digital Drive Strength Selection. Selected as shown in Table 13. For drive strength calculation, see Output Drive Currents on page 31. The drive strength for some pins is preset, not controlled by the DS2-0 pins. The pins that are always at drive strength 7 (100%) include: CPA, DPA, TDO, EMU, and RST_OUT. The drive strength for the ACK pin is always x2 drive strength 7 (100%). Enable on-chip DRAM Regulator. This pin selects whether the internal DRAM is supplied from: 0 = VDD_DRAM; connect VDD_DRAM pins to properly decoupled DRAM power supply 1 = VDD_IO; connect VDD_DRAM pins to bulk and decoupling capacitors only (default)
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
Table 13. Drive Strength/Output Impedance Selection DS2-0 Pins Drive Strength1 Output Impedance 2
000 001 010 011 100 101 (default) 110 111
1 2
Strength 0 (11.1%) Strength 1 (23.8%) Strength 2 (36.5%) Strength 3 (49.2%) Strength 4 (61.9%) Strength 5 (74.6%) Strength 6 (87.3%) Strength 7 (100%)
120 96 70 62 50 40 32 26
CONTROLIMP1 = 0, A/D mode disabled. CONTROLIMP1 = 1, A/D mode enabled.
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Table 14. Pin Definitions--Power, Ground, and Reference Description
VDD VDD_A VDD_IO VDD_DRAM VREF
P P P P I
SCLK_VREF VSS NC
I1 G --
VDD pins for internal logic. VDD pins for analog circuits. Pay critical attention to bypassing this supply. VDD pins for I/O buffers. VDD pins (optional) for internal DRAM; enabled with ENEDREG pin listed in Table 12. Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN, POR_IN, IRQ3-0, FLAG3-0, DMAR3-0, ID2-0, CONTROLIMP1-0, LxDATO3-0P/N, LxCLKOUTP/N, LxDATI3-0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST. VREF can be connected to a power supply or set by a voltage divider circuit as shown in Figure 5. For more information, see Filtering Reference Voltage and Clocks on page 9. System Clock Reference. Connect this pin to a reference voltage as shown in Figure 6. For more information, see Filtering Reference Voltage and Clocks on page 9. Ground pins. No Connect. Do not connect these pins to anything (not to any supply, signal, or each other). These pins are reserved and must be left unconnected.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
1
For more information on SCLK and SCLK_VREF on revision 0.0 silicon, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com).
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an internal pullup or pulldown for the default value. If a strap pin is not connected to an overdriving external pullup, pulldown, or logic load, the DSP samples the default value during reset. If strap pins are connected to logic
Table 15. Pin Definitions--I/O Strap Pins Type (at Reset)
inputs, a stronger external pullup or pulldown may be required to ensure default value depending on leakage and/or low level input current of the logic load. To set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pullup or pulldown. Table 15 lists and describes each of the DSP's strap pins.
Signal
On Pin...
Description
EBOOT
I (pd_0)
BMS
IRQEN
I (pd)
BM
LINK_DWIDTH
I (pd)
TMR0E
EPROM boot. 0 = boot from EPROM immediately after reset (default) 1 = idle after reset and wait for an external device to boot DSP through the external port or a link port Interrupt Enable. 0 = disable and set IRQ3-0 interrupts to level-sensitive after reset (default) 1 = enable and set IRQ3-0 interrupts to edge-sensitive immediately after reset Link Port Input Default Data Width. 0 = 1-bit (default) 1 = 4-bit
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
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Table 15. Pin Definitions--I/O Strap Pins (continued)
On Pin...
Description
SYS_REG_WE
I (pd_0) I (pu) I (pu) I (pu)
BUSLOCK
TM1 TM2 TM3
L1BCMPO L2BCMPO L3BCMPO
SYSCON and SDRCON Write Enable. 0 = one-time writable after reset (default) 1 = always writable Test Mode 1. Do not overdrive default value during reset. Test Mode 2. Do not overdrive default value during reset. Test Mode 3. Do not overdrive default value during reset.
I = input; A = asynchronous; O = output; OD = open drain output; T = Three-State; P = power supply; G = ground; pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0; pu_od_0 = internal pullup 500 on DSP ID=0; pd_m = internal pulldown 5 k on DSP bus master; pu_m = internal pullup 5 k on DSP bus master; pu_ad = internal pullup 40 k; For more pulldown and pullup information, see Electrical characteristics on page 20.
When default configuration is used, no external resistor is needed on the strap pins. To apply other configurations, a 500 resistor connected to VDD_IO is required. If providing external pulldowns, do not strap these pins directly to VSS; the strap pins require 500 resistor straps. All strap pins are sampled on the rising edge of RST_IN (deassertion edge). Each pin latches the strapped pin state (state of the strap pin at the rising edge of RST_IN). Shortly after deassertion of RST_IN, these pins are re-configured to their normal functionality. These strap pins have an internal pull-down resistor, pull-up resistor, or no-resistor (three-state) on each pin. The resistor type, which is connected to the I/O pad, depends on whether RST_IN is active (low) or if RST_IN is de-asserted (high). Table 16 shows the resistors that are enabled during active reset and during normal operation
Table 16. Strap Pin Internal Resistors--Active Reset (RST_IN = 0) Versus Normal Operation (RST_IN = 1) PIN RST_IN = 0 RST_IN = 1
BMS BM TMR0E BUSLOCK L1BCMPO L2BCMPO L3BCMPO
(pd_0) (pd) (pd) (pd_0) (pu) (pu) (pu)
(pu_0) Driven Driven (pu_0) Driven Driven Driven
pd = internal pulldown 5 k; pu = internal pullup 5 k; pd_0 = internal pulldown 5 k on DSP ID=0; pu_0 = internal pullup 5 k on DSP ID=0
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ADSP-TS201S--SPECIFICATIONS
Note that component specifications are subject to change without notice. For information on Link port electrical characteristics, see Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing on page 26.
RECOMMENDED OPERATING CONDITIONS
Parameter Test Conditions Min Typ Max Unit
VDD VDD_A VDD_IO VDD_DRAM TCASE VIH VIL IDD IDD_IO IDD_IO IDD_DRAM
Internal Supply Voltage Analog Supply Voltage I/O Supply Voltage Internal DRAM Supply Voltage Case Operating Temperature High-Level Input Voltage1 Low-Level Input Voltage1 VDD supply current for typical activity2 VDD_IO supply current for typical activity2 (DRAM Internal Regulator Disabled) VDD_IO supply current for typical activity2 (DRAM Internal Regulator Enabled) VDD_DRAM supply current for typical activity2,3
@ VDD, VDD_IO = max @ VDD, VDD_IO = min @ CCLK=500 MHz, VDD=1.0 V, TCASE=25C @ SCLK=100 MHz, VDD_IO=2.5 V, TCASE=25C, ENEDREG=0 @ SCLK=100 MHz, VDD_IO=2.5 V, TCASE=25C, ENEDREG=1 @ CCLK=500 MHz, VDD_DRAM=1.5 V, TCASE=25C, ENEDREG=0
0.95 0.95 2.38 1.425 -40 1.7 -0.5 2.39 0.16 0.83 0.67
1.05 1.05 2.63 1.575 +85 3.63 0.8
V V V V C V V A A A A
VREF Voltage reference SCLK_VREF Voltage reference
1 2
(VDD_IO/2) 5% V (VDD_IO/2) 5%4 V
Applies to input and bidirectional pins. For details on internal and external power calculation issues, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices website. 3 For ENEDREG=1, the internal DRAM supply is used; there is no IDD_DRAM for this condition. 4 If the clock driver voltage > VDD_IO and the clock driver voltage is used to generate SCLK_VREF, this formula becomes: (VCLOCK_DRIVE/2) 5%.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
1
Min
Max
Unit
VOH VOL IIH IIH_PD IIL IIL_PU IIL_PU_AD IOZH IOZH_PD IOZL IOZL_PU IOZL_PU_AD IOZL_OD CIN
High-Level Output Voltage Low-Level Output Voltage1 High-Level Input Current High-Level Input Current Low-Level Input Current Low-Level Input Current Low-Level Input Current Three-State Leakage Current High Three-State Leakage Current High Three-State Leakage Current Low Three-State Leakage Current Low Three-State Leakage Current Low Three-State Leakage Current Low Input Capacitance2,3
@VDD_IO = min, IOH = -2 mA @VDD_IO = min, IOL = 4 mA @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = 0V @VDD_IO = max, VIN = 0V @VDD_IO = max, VIN = 0V @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = 0V @VDD_IO = max, VIN = 0 @VDD_IO = max, VIN = 0 @VDD_IO = max, VIN = 0V @fIN = 1MHz,TCASE = 25C, VIN = 2.5V
2.18 0.4 10 0.76 10 0.76 0.1 10 0.76 10 0.76 0.1 7.6 3
0.4 0.4 0.05 0.4 0.4 0.05 4
V V A mA A mA mA A mA A mA mA mA pF
Parameter name suffix conventions: no suffix = applies to pins without pullup or pull down resistors, _PD = applies to pin types (pd) or (pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD
1 2
Applies to output and bidirectional pins. Applies to all signals. 3 Guaranteed but not tested.
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ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDD)1 . . . -0.3 V to +1.40 V Analog (PLL) Supply Voltage (VDD_A)1 . . . -0.3 V to +1.40 V External (I/O) Supply Voltage (VDD_IO)1 . . . -0.3 V to +3.5 V External (DRAM) Supply Voltage (VDD_DRAM)1-0.3 V to +2.1 V Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.63 V Output Voltage Swing1 . . . . . . . . . . .-0.5 V to VDD_IO +0.5 V Storage Temperature Range1 . . . . . . . . . . .-65C to +150C
1
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-TS201S features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
With the exception of DMAR3-0, IRQ3-0, TMR0E, and FLAG3-0 (input only) pins, all AC timing for the ADSP-TS201S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSP-TS201S processor has few calculated (formula-based) values. For information on AC timing, see General AC Timing on page 21. For information on Link port transfer timing, see Link Port LowVoltage, Differential-Signal (LVDS) Electrical Characteristics and Timing on page 26.
General AC Timing
Timing is measured on signals when they cross the 1.25 V level as described in Figure 10 on page 25. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.25 V and the point that the second signal reaches 1.25 V. The general AC timing data appears in Table 18 and Table 22. The AC asynchronous timing data for the IRQ3-0, DMAR3-0, FLAG3-0, and TMR0E pins appears in Table 17.
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Pulsewidth High (min)
Table 17. AC Asynchronous Signal Specifications (all values in this table are in nanoseconds) Description
1
Pulsewidth Low (min)
IRQ3-0 DMAR3-01 FLAG3-02 TMR0E3
1 2
Interrupt Request DMA Request FLAG3-0 Input Timer 0 Expired
2 x tSCLK ns 2 x tSCLK ns 2xtSCLK ns 4xtSCLK ns
2 x tSCLK ns 2 x tSCLK ns 2xtSCLK ns -
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. For output specifications on FLAG3-0 pins, see Table 22. 3 This pin is a strap option. During reset, an internal resistor pulls the pin low.
Table 18. Reference Clocks Speed Grade (MHz) Clock Cycle Min (ns) Clock Cycle Max (ns) Clock High Min (ns) Clock Low Min (ns) Input Jitter1 Tolerance (ps)
Signal
Type Description
2
CCLK SCLK3,4 TCK
1 2
- I I
Core Clock System Clock Test Clock (JTAG)
500 All All
2.0 Greater of 8 or CCLKx4 Greater of 30 or CCLKx4
12.5 50 -
- - {40% to 60% Duty Cycle} 12 12
- 100 -
Actual input jitter should be combined with ac specifications for accurate timing analysis. CCLK is the internal DSP clock or instruction cycle time. The period of this clock is equal to the System Clock (SCLK) period divided by the System Clock Ratio (SCLKRAT2-0). For information on available internal DSP clock rates, see the Ordering Guide on page 40. 3 For more information, see Table 3 on page 11. 4 For more information, see Clock Domains on page 9.
Table 19. Power-Up Reset Timing Parameter Min Max Units
Timing Requirements tVDD_DRAM1 tVDD_DRAM_RAMP
1
VDD_DRAM Stable After VDD, VDD_A, VDD_IO Stable VDD_DRAM Supply Rise Time
0 0.2
ms ms
Applies only when the internal DRAM regulator is disabled (ENEDREG=0)
tVDD_DRAM
VDD VDD_A VDD_IO
tVDD_DRAM_RAMP
VDD_DRAM
Figure 7. Power-Up Timing
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Table 20. Power-Up Reset Timing
Timing Requirements tRST_PWR tTRST_IN_PWR1 tRST_OUT_PWR
1
RST_IN Deasserted After VDD, VDD_A, VDD_IO, VDD_DRAM (ENEDREG=0), 2 SCLK, and Static/Strap Pins Stable TRST Asserted During Power-Up Reset RST_OUT Deasserted After RST_IN Deasserted 100xtSCLK 1.5
ms ns ms
Switching Characteristic
Applies after VDD, VDD_A, VDD_IO, VDD_DRAM (ENEDREG=0), and SCLK are stable and before RST_IN deasserted.
tRST_IN_PWR
RST_IN
tRST_OUT_PWR
RST_OUT
tTRST_PWR
TRST
SCLK, VDD, VDD_A, VDD_IO, VDD_DRAM STATIC/STRAP PINS
Figure 8. Power-Up Reset Timing Table 21. Normal Reset Timing Parameter Min Max Units
Timing Requirements tRST_IN tSTRAP tRST_OUT RST_IN Asserted RST_IN Deasserted After Strap Pins Stable RST_OUT Deasserted After RST_IN Deasserted 2 1.5 1.5 ms ms ms
Switching Characteristic
tRST_IN
RST_IN
tRST_OUT
RST_OUT
tSTRAP
STRAP PINS
Figure 9. Normal Reset Timing
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Output Disable (max)1 Output Enable (min)1
Table 22. AC Signal Specifications (all values in this table are in nanoseconds) Output Valid (max) Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
ADDR31-0 DATA63-0 MSH MSSD3-0 MS1-0 RD WRL WRH ACK SDCKE RAS CAS SDWE LDQM HDQM SDA10 HBR HBG BOFF BUSLOCK BRST BR7-0 BM IORD IOWR IOEN CPA DPA BMS FLAG3-0 RST_IN TMS TDI TDO TRST
3,4 2 3,4
External Address Bus External Data Bus Memory Select HOST Line Memory Select SDRAM Lines Memory Select for Static Blocks Memory Read Write Low Word Write High Word Acknowledge for Data Hi to Low SDRAM Clock Enable Row Address Select Column Address Select SDRAM Write Enable Low Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Bus Request Host Bus Grant Back Off Request Bus Lock Burst pin Bus Master Debug aid only I/O Read pin I/O Write pin I/O Enable pin Core Priority Access Hi to Low Core Priority Access Low to Hi DMA Priority Access Hi to Low DMA Priority Access Low to Hi Boot Memory Select FLAG pins Global Reset pin Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG)
1.5 1.5 -- 1.5 -- 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 -- -- -- 1.5 1.5 1.5 -- 1.5 -- -- -- -- 1.5 1.5 1.5 1.5 1.5 -- 1.5 1.5 1.5 -- 1.5
0.5 0.5 -- 0.5 -- 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 0.5 0.5 0.5 -- 0.5 0.5 -- -- -- -- 0.5 0.5 0.5 0.5 0.5 -- 0.5 0.5 0.5 -- 0.5
4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 3.6 4.2 4.0 4.0 4.0 4.0 4.0 4.0 4.0 -- 4.0 -- 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 23.5 4.0 23.5 4.0 4.0 -- -- -- 4.0 --
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.0 2.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -- 1.0 -- 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.0 1.0 2.0 1.0 1.0 -- -- -- 1.0 --
1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 -- 1.15 -- 1.15 1.15 -- -- 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 -- -- -- 1.15 --
2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 -- 2.0 -- 2.0 2.0 -- -- 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 -- -- -- 2.0 --
SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK TCK TCK TCK TCK
Acknowledge for Data Low to High 1.5
Multiprocessing Bus Request pins 1.5
24
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Reference Clock
PRELIMINARY TECHNICAL DATA June 2003
For current information contact Analog Devices at 800/262-5643
ADSP-TS201S
Output Disable (max)1 Output Enable (min)1 Output Hold (min)
Table 22. AC Signal Specifications (all values in this table are in nanoseconds) (continued) Output Valid (max)
Input Setup (min)
Input Hold (min)
Name
Description
EMU5 ID2-06 CONTROLIMP1-0 DS2-06 SCLKRAT2-0 ENEDREG JTAG SYS
1
Emulation High to Low Static pins - must be constant
6
-- -- -- -- -- -- 1.5 1.5
-- -- -- -- -- -- 0.5 0.5
3.6 -- -- -- -- -- -- 0.4
2.0 -- -- -- -- -- -- 1.0
1.15 -- -- -- -- -- -- --
2.0 -- -- -- -- -- -- --
TCK or SCLK -- -- -- -- -- SCLK TCK
Static pins - must be constant Static pins - must be constant Static pins - must be constant Static pins - must be constant Strap pins JTAG system pins
6
6
STRAP SYS7,8
9
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual. 2 For input specifications on FLAG3-0 pins, see Table 17. 3 These input pins are asynchronous and therefore do not need to be synchronized to a clock reference. 4 For additional requirement details, see Reset and Booting on page 8. 5 Reference clock depends on function. 6 These pins may change only during reset; recommend connecting it to VDD_IO/VSS. 7 STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO. 8 Specifications applicable during reset only. 9 JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3-0, DMAR3-0, HBR, BOFF, MS1-0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN, BUSLOCK, TMR0E, DATA63-0, ADDR31-0, RD, WRL, WRH, BRST, MSSD3-0, RAS, CAS, SDWE, HBG, BR7-0, FLAG3-0, L0DATOP3-0, L0DATON3-0, L1DATOP3-0, L1DATON3-0, L2DATOP3-0, L2DATON3-0, L3DATOP3-0, L3DATON3-0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP, L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3-0, L0DATIN3-0, L1DATIP3-0, L1DATIN3-0, L2DATIP3-0, L2DATIN3-0, L3DATIP3-0, L3DATIN3-0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2-0, CTRL_IMPD1-0, SCLKRAT2-0, DS2-0, ENEDREG.
REFERENCE CLOCK 1.25V
tSCLK OR tTCK
INPUT SIGNAL 1.25V INPUT SETUP INPUT HOLD
OUTPUT SIGNAL OUTPUT VALID 1.25V OUTPUT HOLD
THREESTATE OUTPUT DISABLE OUTPUT ENABLE
Figure 10. General AC Parameters Timing
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Reference Clock
25
PRELIMINARY TECHNICAL DATA ADSP-TS201S
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June 2003
Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics and Timing
Table 23 and Table 24 with Figure 11 provide the electrical characteristics for the LVDS link ports.
The LVDS link port signal definitions represent all differential signals with a VOD = 0 V level and use signal naming without N (negative) and P (positive) suffixes (see Figure 12).
Table 23. Link Port LVDS Transmit Electrical Characteristics Parameter Test Conditions Min Max Units
VOH VOL |VOD| IOS VOCM
Output Voltage High, VO_P or VO_N Output Voltage Low, VO_P or VO_N Output Differential Voltage Short-circuit Output Current Common Mode Output Voltage
RL = 100 RL = 100 RL = 100 VO_P or VO_N = 0 V VOD = 0 V
1.58 0.92 150 450 +5/- 40 +/- 5 1.38
1.13
V V mV mA mA V
Table 24. Link Port LVDS Receive Electrical Characteristics Parameter Test Conditions Min Max Units
|VID| VICM
Differential Input Voltage Common Mode Input Voltage
100 0.6
600 1.57
mV V
VO_P RL VO_N
VOD = (VO_P - VO_N) (VO_P + VO_N ) 2
VOCM =
Figure 11. Link Ports--Transmit Electrical Characteristics
DIFFERENTIAL PAIR WAVEFORMS LxP V O_N
LxN
VO _P
DIFFERENTIAL VO LTAG E WAVEFORM Lx V OD = 0V V OD = VO _P - V O_N
Figure 12. Link Ports--Signals Definition
26
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PRELIMINARY TECHNICAL DATA June 2003
Link Port--Data Out Timing Table 25. Link Port--Data Out Timing Parameter Min Max Units
For current information contact Analog Devices at 800/262-5643
ADSP-TS201S
Outputs tREO tFEO tLCLKOP tLCLKOH tLCLKOL tCOJT tLDOS
tLDOH
tLACKID tBCMPOV tBCMPOH Inputs tLACKIS
Rising Edge (Figure 13) Falling Edge (Figure 13) LxCLKOUT Period (Figure 14) LxCLKOUT High (Figure 14 LxCLKOUT Low (Figure 14) LxCLKOUT Jitter (Figure 14) LxDATO Output Setup, LCR = 1 and LCR = 1.5 (Figure 15) LxDATO Output Setup, LCR = 2 and LCR = 4 (Figure 15) LxDATO Output Hold, LCR = 1 and LCR = 1.5 (Figure 15) LxDATO Output Hold, LCR = 2 and LCR = 4 (Figure 15) Delay from LxACKI rising edge to first transmission clock edge (Figure 16) LxBCMPO Valid (Figure 16) LxBCMPO Hold (Figure 17).
0.9xLCRxtCCLK1,2 0.4xLCRxtCCLK1,2 0.4xLCRxtCCLK1,2 smaller of 2.53 or 0.25xLCRxtCCLK - 0.151,2,4 smaller of 2.53 or 0.25xLCRxtCCLK - 0.31,2,4 0.25xLCRxtCCLK - 0.151,2,4 0.25xLCRxtCCLK - 0.31,2,4
200 200 1.1xLCRxtCCLK1,2 0.6xLCRxtCCLK1,2 0.6xLCRxtCCLK1,2 -/+70
ps ps ns ns ns ps ns ns ns ns
14xLCRxtCCLK1,2 2xLCRxtCCLK1,2 3xTSW - 0.5
1,2,5
ns ns ns ns
tLACKIH
1 2
LxACKI low setup to guarantee that the trans- 14xLCRxtCCLK1,2 mitter stops transmitting (Figure 17). LxACKI high setup to guarantee that the transmitter continues its transmission without any interruption (Figure 18). LxACKI high hold time (Figure 17). 0.51,2
ns
Timing is relative to the 0 differential voltage (VOD = 0) LCR (Link port Clock Ratio) = 1, 1.5, 2 or 4. tCCLK is the core period 3 The 2.5 value for tLDOS applies for LCLKOUT100 MHz. 4 tLDOS and tLDOH values include LCLKOUT jitter. 5 TSW is a short-word transmission period. For a 4-Bit Link it is 2xLCRxtCCLK and for a 1-Bit Link is 8xLCRxtCCLK ns
VO_P RL VO_N CL_P RL = 100 CL = 0.1pF CL_P = 5pF CL_N = 5pF
tLCLKOP
CL
VOD = 0V LxCLKOUT
CL_N
tCOJT
tLCLKOH
tLCLKOL
tREO
+ VOD| MIN VOD = 0V
tFEO
|
Figure 14. Link Ports--Output Clock
-|VOD| MIN
Figure 13. Link Ports--Differential Output Signals Transition Time
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27
PRELIMINARY TECHNICAL DATA ADSP-TS201S
LxCLKOUT VOD = 0V
For current information contact Analog Devices at 800/262-5643
June 2003
tLDOS tLDOH tLDOS tLDOH
LxDATO VOD = 0V
Figure 15. Link Ports--Data Output Setup and Hold1
1
These parameters are valid for both clock edges
LxCLKOUT VOD = 0V
LxDATO VOD = 0V
tLACKID
LxACKI
tBCMPOV
LxBCMPO
Figure 16. Link Ports--Transmission Start
28
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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ADSP-TS201S
FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD LAST EDGE IN A QUAD WORD LxCLKOUT VOD = 0V
LxDATO VOD = 0V
tLACKIS
tLACKIH
LxACKI
tBCMPOH
LxBCMPO
Figure 17. Link Ports--Transmission End and Stops
LAST EDGE IN A QUAD WORD
LxCLKOUT VOD = 0V
LxDATO VOD = 0V
tLACKIS
tLACKIH
LxACKI
Figure 18. Link Ports--Back to Back Transmission
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29
PRELIMINARY TECHNICAL DATA ADSP-TS201S
Link Port--Data In Timing Table 26. Link Port--Data In Timing Parameter Min Max Units
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June 2003
Inputs tLCLKIP tREI tFEI tLDIS tLDIH tBCMPIS tBCMPIH
1 2
LxCLKIN Period (Figure 21) Rising Edge (Figure 20) Falling Edge (Figure 20) LxDATI Input Setup (Figure 21) LxDATI Input Hold (Figure 21) LxBCMPI Valid (Figure 19) LxBCMPI Hold (Figure 19)
0.9xtCCLK1 400 400 0.21 0.21 2xLCRxtCCLK1,2 2xLCRxtCCLK1,2
ns ps ps ns ns ns ns
Timing is relative to the 0 differential voltage (VOD = 0) LCR (Link port Clock Ratio) = 1, 1.5, 2 or 4. tCCLK is the core period
FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD LxCLKIN VOD = 0V
LxDATI VOD = 0V
tBCMPIS
tBCMPIH
LxBCMPI
Figure 19. Link Ports--Last Received Quad Word
tREI
+ VOD MIN VOD = 0V
tFEI
LxCLKIN VOD = 0V
tLCLKIP
|
|
-|VOD| MIN
tLDIS tLDIH tLDIS tLDIH
Figure 20. Link Ports--Differential Input Signals Transition Time
LxDATI VOD = 0V
Figure 21. Link Ports--Data Input Setup and Hold1
1
These parameters are valid for both clock edges
30
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PRELIMINARY TECHNICAL DATA June 2003
Output Drive Currents
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ADSP-TS201S
STRENGTH 2
OUTPUT PIN CURRENT - mA
Figure 22 through Figure 29 show typical I-V characteristics for the output drivers of the ADSP-TS201S processor. The curves in these diagrams represent the current drive capability of the output drivers as a function of output voltage over the range of drive strengths. For complete output driver characteristics, refer to the DSP's IBIS models, available on the Analog Devices website (www.analog.com).
STRENGTH 0 30 25 20 15
OUTPUT PIN CURRENT - mA
80 IOL 60 40 20 0 -20 -40 VDD_IO -60 -80 -100 0 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE - V 2.4 2.8 IOH VDD_IO = 2.375V, +85C VDD_IO = 2.625V, -40C VDD_IO = 2.5V, +25C V Y = 2.625V, -40C R NA I +25C M2.5V, =
DD_IO
EL = 2.375V, +85C PR
VDD_IO
I
IOL VDD_IO = 2.625V, -40C VDD_IO = 2.5V, +25C
10 5 0 -5 -10 VDD_IO -15 -20 -25 -30 0 0.4
VDD_IO = 2.375V, +85C V EL = 2.375V, +85C PR
DD_IO
I = 2.5V, +25C
Y AVR = 2.625V, -40C N MI
DD_IO
Figure 24. Typical Drive Currents at Strength 2
STRENGTH 3 125
IOH
OUTPUT PIN CURRENT - mA
100 75
IOL
0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE - V
2.4
2.8
50 25 0 -25 -50 VDD_IO -75 VDD_IO = 2.375V, +85C
VDD_IO = 2.625V, -40C VDD_IO = 2.5V, +25C
Figure 22. Typical Drive Currents at Strength 0
STRENGTH 1 60 50 40
OUTPUT PIN CURRENT - mA
IM V EL = 2.5V, +25C PR = 2.375V, +85C
DD_IO
Y V AR = 2.625V, -40C IN
DD_IO
IOL
30 20 10 0 -10 -20 -30 -40 -50 -60 -70 0 0.4 VDD_IO VDD_IO = 2.375V, +85C
VDD_IO = 2.625V, -40C VDD_IO = 2.5V, +25C
-100 -125 0 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE - V
IOH
EL = 2.375V, +85C PR
VDD_IO
I
RY NA I = M2.5V, +25C
2.4
2.8
VDD_IO = 2.625V, -40C
Figure 25. Typical Drive Currents at Strength 3
STRENGTH 4 140 120 IOL
IOH
OUTPUT PIN CURRENT - mA
100 80 60 40 20 0 -20 -40 -60 V DD_IO -80 -100 -120 -140 -160 0 0.4 0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE - V 2.4 2.8 IOH VDD_IO = 2.375V, +85C VDD_IO = 2.625V, -40C VDD_IO = 2.5V, +25C
0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE - V
2.4
2.8
Figure 23. Typical Drive Currents at Strength 1
EL = 2.375V, +85C PR
VDD_IO = 2.5V, +25C
IM
Y AVR = 2.625V, -40C IN
DD_IO
Figure 26. Typical Drive Currents at Strength 4
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31
PRELIMINARY TECHNICAL DATA ADSP-TS201S
160 140 120 100 80 60 40 20 0 -20 -40 IOL VDD_IO = 2.625V, -40C VDD_IO = 2.5V, +25C
For current information contact Analog Devices at 800/262-5643
June 2003
STRENGTH 5
Test Conditions
OUTPUT PIN CURRENT - mA
The ac signal specifications (timing parameters) appear Table 22 on page 24. These include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 30.
VDD_IO = 2.375V, +85C
-60 -80 VDD_IO = 2.375V, +85C -100 -120 -140 -160 -180 0 0.4
I V L = 2.5V, +25C RE P
DD_IO
Y VR = 2.625V, -40C NA MI
DD_IO
INPUT OR OUTPUT
1.25V
1.25V
IOH
Figure 30. Voltage reference levels for AC measurements (except output enable/disable)
0.8 1.2 1.6 2.0 OUTPUT PIN VOLTAGE - V
2.4
2.8
REFERENCE SIGNAL
Figure 27. Typical Drive Currents at Strength 5
STRENGTH 6 180 160 IOL 140 120 VDD_IO = 2.625V, -40C 100 80 VDD_IO = 2.5V, +25C 60 40 VDD_IO = 2.625V, -40C 20 VDD_IO = 2.375V, +85C 0 -20 VDD_IO = 2.5V, +25C -40 -60 -80 VDD_IO = 2.375V, +85C -100 -120 -140 -160 IOH -180 -200 -220 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 OUTPUT PIN VOLTAGE - V
tMEASURED_DIS tDIS
VOH (MEASURED) VOH (MEASURED) - VOL (MEASURED) VOL (MEASURED) +
tMEASURED_ENA tENA
V V 1.65V 0.85V
OUTPUT PIN CURRENT - mA
tDECAY
OUTPUT STOPS DRIVING
tRAMP
OUTPUT STARTS DRIVING
I EL PR
Y AR N MI
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.25V
Figure 31. Output Enable/Disable Output Disable Time
Figure 28. Typical Drive Currents at Strength 6
STRENGTH 7 220 200 IOL 180 160 140 VDD_IO = 2.625V, -40C 120 100 VDD_IO = 2.5V, +25C 80 60 40 VDD_IO = 2.625V, -40C 20 VDD_IO = 2.375V, +85C 0 -20 VDD_IO = 2.5V, +25C -40 -60 -80 -100 VDD_IO = 2.375V, +85C -120 -140 -160 IOH -180 -200 -220 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 OUTPUT PIN VOLTAGE - V
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the following equation: tDECAY = (CLV)/IL The output disable time tDIS is the difference between tMEASURED_DIS and tDECAY as shown in Figure 31. The time tMEASURED_DIS is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with V equal to 0.4 V.
Output Enable Time
OUTPUT PIN CURRENT - mA
L RE P
I
Y AR N MI
Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The time for the voltage on the bus to ramp by V is dependent on the capacitive load, CL, and the drive current, ID. This ramp time can be approximated by the following equation: tRAMP = (CLV)/ID
Figure 29. Typical Drive Currents at Strength 7
32
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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ADSP-TS201S
STRENGTH 1 (VDD _IO = 2.5V)
RISE AND FALL TIMES - ns
The output enable time tENA is the difference between tMEASURED_ENA and tRAMP as shown in Figure 31. The time tMEASURED_ENA is the interval from when the reference signal switches to when the output voltage ramps V from the measured three-stated output level. tRAMP is calculated with test load CL, drive current ID, and with V equal to 0.4 V.
Capacitive Loading
25
20
15
Output valid and hold are based on standard capacitive loads: 30 pF on all pins (see Figure 32). The delay and hold specifications given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. Figure 33 through Figure 40 show how output rise time varies with capacitance. Figure 41 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on page 32.) The graphs of Figure 33 through Figure 41 may not be linear outside the ranges shown.
RISE TIME
10
y = 0.1349x + 1.9955
P
L RE
IM
R IN A
Y
FALL TIME y = 0.1163x + 1.4058
5
0
0
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE - pF
Figure 34. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 1
STRENGTH 2
TO OUTPUT PIN
50 1.25V 30pF
25
(VDD_IO = 2.5V)
RISE AND FALL TIMES - ns
20
Figure 32. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
STRENGTH 0 25 (VDD_IO = 2.5V)
15
10
RISE TIME
y = 0.1304x + 0.8427
P
I EL R
Y AR N MI
FALL TIME y = 0.1144x + 0.7025
RISE AND FALL TIMES - ns
20
RISE TIME
5
15
y = 0.2015x + 3.8869
10
LI RE P
RY NA FALL TIME MI
y = 0.174x + 2.6931
0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE - pF
Figure 35. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 2
5
STRENGTH 3 25
0
(VDD_IO = 2.5V)
0
10
20
30
40
50
60
70
80
90
100
RISE AND FALL TIMES - ns
LOAD CAPACITANCE - pF
20
Figure 33. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 0
15
10
RISE TIME
y = 0.1082x + 1.3123
P
IM EL R
Y AR IN
FALL TIME y = 0.0912x + 1.2048
5
0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE - pF
Figure 36. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 3
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PRELIMINARY TECHNICAL DATA June 2003
25
For current information contact Analog Devices at 800/262-5643
ADSP-TS201S
STRENGTH 7 (VDD_IO = 2.5V)
STRENGTH 4 (VDD_IO = 2.5V)
25
RISE AND FALL TIMES - ns
RISE AND FALL TIMES - ns
20
20
15
10
Y AR IN LIM E RISE TIME R P
y = 0.1071x + 0.9877
15
10
RISE TIME
P
IM EL R
Y AR IN
y = 0.0907x + 1.0071
5
FALL TIME y = 0.0798x + 1.0743
5
FALL TIME y = 0.09x + 0.3134
0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE - pF
0
0
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE - pF
Figure 37. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 4
STRENGTH 5 25 (VDD_IO = 2.5V)
Figure 40. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 7
15 STRENGTH 0-7 (V DD_IO = 2.5V) 0
RISE AND FALL TIMES - ns
20
15
10
RISE TIME
P
LI RE
MI
Y AR N
OUTPUT VALID - ns
10
5
E PR
LI
N MI
Y AR
1 2 3 4 5 6 7
y = 0.1001x + 0.7763
5
FALL TIME y = 0.0793x + 0.8691
0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE - pF
0 0 10 20 30 40 50 60 70 80 LOAD CAPACITANCE - pF 90 100
Figure 38. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 5
1
Figure 41. Typical Output Valid (VDD_IO = 2.5 V) vs. Load Capacitance at Max Case Temperature and Strength 0-71
The line equations for the output valid versus load capacitance are: Strength 0: y = 0.0956x + 3.5662 Strength 1: y = 0.0523x + 3.2144 Strength 2: y = 0.0433x + 3.1319 Strength 3: y = 0.0391x + 2.9675 Strength 4: y = 0.0393x + 2.7653 Strength 5: y = 0.0373x + 2.6515 Strength 6: y = 0.0379x + 2.1206 Strength 7: y = 0.0399x + 1.9080
STRENGTH 6 25 (VDD_IO = 2.5V)
RISE AND FALL TIMES - ns
20
15
10
RISE TIME
P
IM EL R
RY NA I
Environmental Conditions
y = 0.0946x + 1.2187
The ADSP-TS201S processor is rated for performance over the extended commercial temperature range, TCASE = -40C to 85C.
FALL TIME y = 0.0906x + 0.4597
5
Thermal Characteristics
0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE - pF
Figure 39. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 2.5 V) vs. Load Capacitance at Strength 6
The ADSP-TS201S processor is packaged in a 25 mm x 25 mm thermally enhanced Ball Grid Array (BGA_ED). The ADSP-TS201S processor is specified for a case temperature (TCASE). To ensure that the TCASE data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. 34
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PRELIMINARY TECHNICAL DATA June 2003
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ADSP-TS201S
Table 27 shows the thermal characteristics of the 25 mm x 25 mm BGA_ED package.
Table 27. Thermal Characteristics for 25 mm x 25 mm Package Parameter Condition Typical Units
JA JC JB
Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s - -
19.6 15.4 13.7 0.7 8.3
C/W C/W C/W C/W C/W
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PRELIMINARY TECHNICAL DATA June 2003
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ADSP-TS201S
576-BALL BGA_ED PIN CONFIGURATIONS Table 28. 576-Ball (25 mm x 25 mm) BGA_ED Pin Assignments Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24
VSS DATA51 VSS DATA49 DATA43 DATA41 DATA37 DATA33 DATA29 DATA25 DATA23 DATA19 DATA15 DATA11 DATA9 DATA5 DATA1 WRL ADDR30 ADDR28 ADDR22 VSS ADDR21 VSS DATA61 DATA62 DATA57 DATA58 VSS VDD_IO VSS VDD_IO VSS VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VSS VDD_IO VSS VDD_IO VSS ADDR15 ADDR14 ADDR11 ADDR10
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24
DATA53 VSS VSS DATA50 DATA44 DATA42 DATA38 DATA34 DATA30 DATA26 DATA24 DATA20 DATA16 DATA12 DATA10 DATA6 DATA2 WRH ADDR31 ADDR29 ADDR23 VSS VSS ADDR18 DATA63 MS1 DATA59 DATA60 VDD_IO VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO ADDR13 ADDR12 ADDR9 ADDR8
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24
VSS VSS VSS DATA52 DATA47 DATA45 DATA39 DATA35 DATA31 DATA27 DATA21 DATA17 VSS DATA13 DATA7 DATA3 ACK RD ADDR26 ADDR24 ADDR20 VSS VDD_IO VDD_IO MSSD1 VSS MS0 BMS VSS VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO ADDR7 ADDR6 ADDR5 ADDR4
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24
DATA55 DATA56 DATA54 VSS DATA48 DATA46 DATA40 DATA36 DATA32 DATA28 DATA22 DATA18 VSS DATA14 DATA8 DATA4 DATA0 BRST ADDR27 ADDR25 VSS ADDR19 ADDR17 ADDR16 VSS MSH MSSD3 SCLKRAT0 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO ADDR3 ADDR2 ADDR1 ADDR0
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PRELIMINARY TECHNICAL DATA June 2003
Pin# Signal Name
For current information contact Analog Devices at 800/262-5643
ADSP-TS201S
Pin# Signal Name
Table 28. 576-Ball (25 mm x 25 mm) BGA_ED Pin Assignments (continued) Pin# Signal Name Pin# Signal Name
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24
RAS CAS VSS VREF VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VSS L0ACKO L0BCMPI L0DATI0_N L0DATI0_P ID0 VSS VDD_A VDD_A VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO L0DATO2_N L0DATO2_P L0CLKON L0CLKOP
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24
SDA10 SDCKE LDQM HDQM VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO L0DATI1_N L0DATI1_P L0CLKINN L0CLKINP SCLK SCLK_VREF VSS BM VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO L0DATO1_N L0DATO1_P L0DATO0_N L0DATO0_P
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24
SDWE BR0 BR1 BR2 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO L0DATI3_N L0DATI3_P L0DATI2_N L0DATI2_P VSS SCLK SCLK_VREF BR7 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_DRAM VDD_DRAM VDD_IO NC VSS L0BCMPO L0ACKI
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24
BR3 SCLKRAT1 BR5 BR6 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO VSS VSS L0DATO3_N L0DATO3_P RST_IN SCLKRAT2 BR4 DS0 VSS VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VSS L1DATI0_N L1DATI0_P L1ACKO L1BCMPI
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PRELIMINARY TECHNICAL DATA June 2003
Pin# Signal Name
For current information contact Analog Devices at 800/262-5643
ADSP-TS201S
Pin# Signal Name
Table 28. 576-Ball (25 mm x 25 mm) BGA_ED Pin Assignments (continued) Pin# Signal Name Pin# Signal Name
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24
MSSD0 RST_OUT ID2 DS1 VDD_IO VDD VDD VSS VSS VDD VDD_DRAM VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO L1CLKINN L1CLKINP L1DATI1_N L1DATI1_P FLAG2 FLAG1 IRQ3 VSS IRQ0 IOEN DMAR0 HBR L3BCMPO L3DATO1_N L3DATO3_N VSS L3DATI2_N L3DATI1_N NC L2DATO0_N L2CLKON L2DATO3_N L2CLKINN L2DATI1_N VSS L1BCMPO L1DATO0_N L1DATO0_P
V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
MSSD2 DS2 POR_IN CONTROLIMP1 VSS VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO L1DATI3_N L1DATI3_P L1DATI2_N L1DATI2_P VSS VSS VSS NC IRQ2 IRQ1 DMAR1 HBG L3ACKI L3DATO1_P L3DATO3_P VSS L3DATI2_P L3DATI1_P VSS L2DATO0_P L2CLKOP L2DATO3_P L2CLKINP L2DATI1_P L2ACKO VSS VDD_IO VDD_IO
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24
CONTROLIMP0 ENEDREG TDI TDO VDD_IO VDD VDD VDD VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD_DRAM VDD_DRAM VDD VDD VDD VDD_IO L1CLKON L1CLKOP L1DATO3_N L1DATO3_P FLAG0 VSS VDD_IO TMS IOWR DMAR2 CPA BOFF L3DATO0_N L3CLKON L3DATO2_N L3DATI3_N L3CLKINN L3DATI0_N L3ACKO L2BCMPO L2DATO1_N L2DATO2_N L2DATI3_N L2DATI2_N L2DATI0_N VDD_IO VSS L1ACKI
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24
EMU TCK TMR0E FLAG3 VSS VDD_IO VSS VDD_IO VSS VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VSS VDD_IO VSS VDD_IO VSS L1DATO1_N L1DATO1_P L1DATO2_N L1DATO2_P VSS ID1 VDD_IO TRST IORD DMAR3 DPA BUSLOCK L3DATO0_P L3CLKOP L3DATO2_P L3DATI3_P L3CLKINP L3DATI0_P L3BCMPI L2ACKI L2DATO1_P L2DATO2_P L2DATI3_P L2DATI2_P L2DATI0_P VDD_IO L2BCMPI VSS
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2 1 3 4 5
For current information contact Analog Devices at 800/262-5643
ADSP-TS201S
24
576-BALL BGA_ED PIN CONFIGURATIONS1 (TOP VIEW, SUMMARY)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD VSS VDD_IO VDD_DRAM VDD_A VREF KEY: SIGNAL VDD
TOP VIEW
1
For a more detailed pin summary diagram, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com)
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ADSP-TS201S
OUTLINE DIMENSIONS
The ADSP-TS201S processor is available in a 25 mm 25 mm, 576-ball metric thermally enhanced Ball Grid Array (BGA_ED) package with 24 rows of balls (BP-576).
576-BALL BGA_ED (BP-576)
25.20 25.00 24.80
24 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 B A C E G J L N R U W AA AC
1.25 1.00 0.75
A1 BALL INDICATOR 23.00 BSC SQ
1.00 BSC
D F H K M P
25.20 25.00 24.80
1.00 BSC SQ BALL PITCH
T V Y AB AD
1.25 1.00 0.75
1.00 BSC
25.20 25.00 SQ 24.80
TOP VIEW
DETAIL A 3.10 MAX 0.97 BSC
BOTTOM VIEW
1.60 MAX 0.60 0.50 0.40
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. THE ACTUAL POSITION OF THE BALL GR ID IS WITHIN 0.25m m OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 4. CENTER DIMENSIONS ARE N OMINAL. 5. THIS PACKAGE C ONFORMS WITH TH E JEDEC MS-034 SPECIFICATION.
SEATING PLANE BALL DIAMETER
0.75 0.65 0.55
0.20 MAX
DETAIL A
ORDERING GUIDE Table 29. Case Temperature Range Instruction Rate5 On-chip DRAM Operating Voltage
Part Number1,2,3,4
Package
ADSP-TS201SABP-ENG
-40C to 85C
500 MHz
24Mbit
1.0 VDD 2.5 VDD_IO 1.5 VDD_DRAM
(BP-576)6
1 2
S indicates 1.0/2.5 V supplies. A indicates -40C to 85C temperature. 3 BP indicated thermally enhanced Ball Grid Array (BGA_ED) package. 4 -ENG indicates engineering grade product. 5 The instruction rate is the same as the internal DSP clock (CCLK) rate. 6 The BP-576 package measures 25mm x 25mm.
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